IonQ Says Its Real-Time Error Decoder Adds as Little as 0.02% Delay. The Paper Ran on a MacBook Pro, Against Simulated Qubits, and Its Own Worst Case Is 11.53%

by Arash Shirazi · September 25, 2026

Quantum Computing Correspondent, Frontier Tech Wire

IonQ (NYSE: IONQ) said on Sept. 22 that its researchers had built and tested what the company calls the industry's first end-to-end real-time quantum error correction decoder running on a single standard off-the-shelf central processing unit, and that under standard operational noise the decoder introduced as little as 0.02% of 'stretch' time. The release, datelined College Park, Md., describes benchmark circuits simulating up to 408 logical qubits across 88 memory blocks and magic-state factories, executing more than 31.5 million individual quantum operations. Every one of those figures is in the paper the release links to (the 31.5 million corresponds to the 31,548,792 syndrome-extraction cycles the paper's Table I lists for that circuit across all blocks). So is a good deal that the release leaves out.

The paper is arXiv:2608.25027, 'Real-time decoder for a MegaQuOp quantum computer using a single CPU', by Min Ye, Andrii Maksymov and Nicolas Delfosse of IonQ. The arXiv listing shows it was submitted on Aug. 25, 2026 and revised on Sept. 3; the version 2 PDF carries an internal date of Sept. 4. The release, which says IonQ 'today announced a major milestone', is dated Sept. 22, four weeks after the preprint first appeared. Nothing in the listing indicates peer review.

The most important word in the paper is 'simulate'. The authors write that 'We simulate all three benchmark workloads using the circuit-level noise model' of IonQ's earlier walking cat architecture paper, 'in which both syndrome extraction and CM are noisy.' The syndrome data the decoder processes were generated by a classical simulation of a fault-tolerant trapped-ion machine, not measured on any IonQ processor. The release's phrase 'benchmark circuits simulating up to 408 logical qubits' is accurate, but no trapped-ion device with 408 logical qubits exists; the company's own Aug. 5 second-quarter release spoke of 'powerful strides towards demonstrating our 256-qubit quantum computer'.

The hardware in the experiment is the classical side. 'All decoding benchmarks are performed on a single 2024 Apple M4 Max CPU in a MacBook Pro,' the paper states, using 12 of the chip's 16 cores, eight for the error decoder and four for the outcome decoder. That is the 'single standard off-the-shelf' CPU of the headline. The point is a fair one: decoders for superconducting machines have needed FPGAs, GPUs or ASICs to keep up with microsecond cycle times, and a laptop-class processor keeping pace with a trapped-ion machine is a meaningful claim about classical overhead. But it is a claim about a laptop and a simulator.

The timing depends on an assumption about how slowly the quantum computer runs. 'Assuming a trapped-ion architecture with 1 to 5 ms cycle time, the decoding delay stretches the computation by less than 0.3% at pCNOT = 10−4 and less than 12% at pCNOT = 5 × 10−4 for all workloads studied,' the abstract says. The authors 'use 1 ms/SEC as a representative long-term trapped-ion hardware timescale and 5 ms/SEC as a representative near-term timescale', where a SEC is one round of syndrome extraction. The 408-logical-qubit workload the release leads with is the one given the slower 5 ms budget.

That is where the 0.02% comes from, and where the release stops. In the paper's Table IV, the Heisenberg n266 circuit of 408 logical qubits at pCNOT of 1 × 10−4 with a 5 ms budget shows a stretch of 0.02%; the same circuit at 5 × 10−4 shows 0.72%. Table II, for a 102-logical-qubit circuit on the tighter 1 ms budget, runs from 0.24% to 11.53%; Table III runs from 0.18% to 10.25%. The release's 'as little as 0.02%' is the best cell in three tables. The paper's own summary, 'less than 12%' at the higher noise rate, does not appear in the release.

The two noise rates are not arbitrary. The paper describes pCNOT between 5 × 10−4 and 10−4 as a range 'which has been achievable over small trapped ion devices'. The lower figure is a two-qubit error of one in ten thousand; IonQ's boilerplate says it 'achieved 99.99% two-qubit gate fidelity' in 2025, the same number the other way round. Whether that holds across the 11,680 physical qubits the simulated architecture assumes is exactly what a simulation cannot answer.

The release also gives the decoder a broader validation than the paper claims. 'This achievement validates a core pillar of IonQ's proprietary Walking Cat architecture and confirms that classical hardware overhead does not need to scale exponentially as quantum systems grow wider in logical qubits or deeper in operations,' the company writes. The paper's conclusion is scoped: 'a single CPU is sufficient for the workloads studied here, spanning 102–408 logical qubits at realistic physical error rates'. The authors also note that 'rare convergence failures can also occur', a caveat the release does not carry.

Two quotations in the release are reproduced in full. 'Successfully validating real-time decoding across hundreds of logical qubits and over millions of logical operations is an important milestone. Moreover, the fact that our decoder runs on a single CPU provides a practical path to commercial-scale fault-tolerant quantum computing' said Nicolas Delfosse, paper co-author and quantum research lead at IonQ. 'IonQ is enabling cost-effective quantum system scaling through direct verification of each component,' said John Gamble, Vice President at IonQ Architecture. 'Empirical evidence like this supports our vision for fault tolerance where time-to-solution, cost-to-solution, and energy-to-solution are always our North Star.' The empirical evidence is timing data from a classical program.

None of this makes the work trivial. The paper's introduction states that 'no end-to-end real-time decoding of a universal quantum computation at scale has been demonstrated' before, and lists the prior art, including offline decoding of 760 logical CZ gates over distance-3 logical qubits. Decoding all logical qubits, all logical operations and the magic-state factories in one pipeline, with detector error models generated on the fly, is a harder problem than decoding a memory experiment. The 'first' in the headline is a first in software.

IonQ's Aug. 5 release reported second-quarter revenue of $80.1 million, up 287% year on year, a GAAP net loss of $1,867.7 million, an adjusted EBITDA loss of $120.3 million, and cash, cash equivalents and investments of $3.0 billion at June 30, or $2.0 billion pro forma for the SkyWater acquisition, with full-year 2026 revenue guidance of $280 million to $290 million. That release said the company had 'made powerful strides towards demonstrating our 256-qubit quantum computer and publishing results for our quantum error correction technology on our hardware.' The Sept. 22 paper is not that hardware result.

The release frames the decoder as 'a key technological foundation for IonQ's roadmap beyond 256 physical qubits toward industrial-scale platforms controlling thousands of qubits.' The link between a decoder benchmarked against simulated syndromes and a roadmap for physical machines runs through the assumptions above: cycle time, noise rate and noise model. The paper reports no run against data from an IonQ trapped-ion system, and this desk found no such claim in the release.

Several details are in neither document. The paper does not state the wall-clock duration of the full simulation or how the M4 Max compares with the server hardware a deployed system would use. The release does not say whether the decoder has been connected to any Forte or Tempo system, and gives no date for doing so.

What comes next is the hardware experiment the company has been promising. Until IonQ publishes error-correction results measured on its own ions with the decoder in the loop, the Sept. 22 announcement should be read as what the paper says it is: a demonstration that the classical bottleneck can be managed, under stated assumptions, for an architecture that has yet to be built at the scale simulated. The company did not disclose whether a journal submission is planned.