Quantinuum preprint reports a fault-tolerant architecture validated on its 98-qubit Helios processor
Quantinuum researchers have posted experimental results for a fault-tolerant quantum computing architecture built around a code they call C4-Helix, run on Helios, the company's 98-qubit trapped-ion processor. The work was posted to arXiv as a preprint on Sept. 2, 2026, under the title "Experimental validation of a compact fault-tolerant architecture for trapped ions," and was summarised for the trade audience by Quantum Computing Report on Sept. 9.
The code at the centre of the paper is written in the standard stabiliser notation as [[20, 2, 6]]: twenty physical qubits encoding two logical qubits, with a code distance of six. Quantum Computing Report describes it as a concatenated symplectic double code that pairs a [[10, 2, 3]] twisted toric code with a [[4, 2, 2]] block code. In plain terms, it is a layered construction that trades a small number of physical qubits for a protected pair of logical ones, rather than the one-logical-qubit-per-large-patch arrangement familiar from surface-code work.
Before any of the numbers: this is a preprint. It has not been through peer review, and the figures reported here should be read as measurements the authors themselves made and reported, not as independently refereed results. The arXiv listing names Noah Berthusen as lead author on a paper with fourteen authors. If a peer-reviewed version appears with revised figures, those are the numbers that will count.
With that caveat attached, the abstract reports three principal results. Repeated quantum error correction was performed with an error of 4.6 x 10^-5 per logical qubit per QEC cycle, with an asymmetric uncertainty band running from 2.0 x 10^-5 to 1.08 x 10^-4 on the authors' stated bounds of plus 6.2 and minus 2.6 in the same units. The complete Clifford group was benchmarked on the two logical qubits of a single codeblock under active error correction, yielding an error of 2.8 x 10^-4 per two-qubit logical Clifford gate, with bounds of plus 1.0 and minus 1.6 in units of 10^-4.
The third result is an interface rather than a memory or gate figure. The authors demonstrate what they describe as a fault-tolerant chain-map interface between C4-Helix and a distance-5 surface code, and use it to prepare a heterogeneous three-logical-qubit GHZ state with a fidelity lower bound of 99.925 percent, with bounds of plus 0.068 and minus 0.245 percentage points. That matters because a practical machine will almost certainly need to move information between codes tuned for different jobs, and demonstrating a working bridge between two code families is a different problem from making either one work alone.
The error bars deserve attention rather than a footnote. On the memory result, the top of the uncertainty band, 1.08 x 10^-4, is more than twice the central value of 4.6 x 10^-5; on the GHZ fidelity, the downside bound of 0.245 percentage points is roughly three and a half times the upside bound of 0.068. These are early-regime measurements with limited statistics, and quoting the central values alone overstates how tightly they are pinned down.
It is worth being explicit about what kind of improvement is being claimed, because this is where quantum results are most often misread. None of these figures is a wall-clock speed measurement. Nothing in the abstract claims that a computation finished faster than it would have on other hardware or on a classical machine. These are error rates and fidelities. They speak to how long a computation can run before noise destroys it, which is a precondition for speed advantages rather than a demonstration of one.
On the question of baselines, the abstract states that in each case the encoded implementation outperforms its corresponding unencoded physical baseline without relying on postselection. The postselection point is not a throwaway. Some early error-correction demonstrations improve their headline numbers by discarding runs in which detectors flagged a problem, which inflates the apparent fidelity at the cost of throughput. The authors say they did not do that here.
Quantum Computing Report's Sept. 9 write-up adds figures not present in the abstract. It puts the two-qubit logical Clifford result at a 4.28-fold improvement over an unencoded physical operation error of 1.2 x 10^-3, and states that the architecture achieves a 3.5-fold reduction in spatial qubit overhead compared with traditional rotated surface codes of equivalent distance, using Quantinuum's reconfigurable two-dimensional ion shuttling to implement non-planar torus topologies. The same write-up lists larger members of the code family as [[60, 2, 12]] and [[100, 2, 18]]. Those overhead and improvement ratios are the publication's characterisation of the work, and readers should weigh them as such.
The abstract also contains a forward-looking claim that is explicitly a simulation rather than a measurement: circuit-level simulations, the authors write, indicate that improvements in physical fidelity would bring the same architecture into the 10^-6 to 10^-8 logical-error regime targeted for early fault-tolerant computation. That is a modelled projection conditional on hardware getting better, and it is not something the Helios runs demonstrated.
One thing the abstract does not report is a non-Clifford or magic-state result, even though it names access to non-Clifford resources as one of the things a complete architecture must orchestrate. The demonstrated components, on the abstract's own account, are repeated error correction, the Clifford group on two logical qubits, and the chain-map interface to a surface code. Whether the non-Clifford piece is addressed in the body of the paper is a separate question from what the abstract advertises.
The authors' own framing is that the results establish C4-Helix as a hardware-validated fault-tolerant architecture rather than a bare quantum memory. That is a claim about category as much as about numbers, and it is the part of the paper most likely to be contested. What would settle it is peer review, replication by groups without a commercial stake in the outcome, and evidence that the larger code variants behave on real hardware the way the design says they should.
