The Fidelity Tax: Rigetti's Chiplet Ladder Shows What Superconducting Scale Actually Costs
Buried in Rigetti Computing's August 6 second-quarter release is the cleanest public illustration of the central problem in superconducting quantum hardware: what happens to quality when you add quantity. The company disclosed median two-qubit gate fidelity of roughly 99.1% on its flagship 108-qubit Cepheus-1-108Q system, against approximately 99.6% at the 36-qubit level and 99.8% at nine qubits.
That ladder is the whole architecture argument in three numbers. Rigetti builds large systems by tiling small ones — Cepheus-1-108Q comprises twelve interconnected nine-qubit superconducting chiplets, following a 36-qubit predecessor made of four, as trade outlet TECHi documented in its analysis of the approach. Chiplets sidestep the yield collapse that plagues monolithic chips as they grow, but each interconnect and each additional tile adds crosstalk, calibration drift and error channels that show up as fidelity erosion.
The gap between 99.6% and 99.1% sounds small and is not. Error rates compound with circuit depth, so a roughly fivefold difference in per-gate error translates into dramatically shorter usable circuits before noise swamps the signal. TECHi framed the decline between the 36-qubit and 108-qubit systems as the central analytical question hanging over chiplet scaling — whether the penalty is a fixed cost of modularity or an engineering problem that yields to iteration.
Rigetti's answer is that it yields. Chief executive Subodh Kulkarni said in the second-quarter release that the company's 'open modular approach, superconducting gate-based architecture, and chiplet-based scaling strategy continue to differentiate' its position. The company's stated three-year technology roadmap targets approximately 1,000 qubits at roughly 99.9% two-qubit fidelity with gate speeds under 50 nanoseconds — up from about 99.9% single-qubit fidelity and roughly 60-nanosecond gates today.
Reaching that target means improving error rates by close to an order of magnitude while multiplying tile count roughly tenfold, simultaneously. Every element of that depends on manufacturing repeatability: identical chiplets, consistent junction parameters, reliable interconnects and packaging that survives repeated thermal cycling to millikelvin temperatures. It is a semiconductor process problem wearing a physics costume, which is why control of fabrication has become a strategic question across the sector.
Rigetti fabricates its own superconducting processors, and it has been assembling outside support for that footprint. The company has disclosed a letter of intent with the U.S. Department of Commerce for up to $100 million in funding, a planned £100 million investment in the United Kingdom over several years, and collaboration with HPE and the Pittsburgh Supercomputing Center on hybrid quantum-classical systems, per its second-quarter release. The 108-qubit machine itself reached general availability in April, according to The Quantum Insider.
The financial frame around the engineering is unusually forgiving by small-cap standards. Rigetti reported second-quarter revenue of $5.1 million, an operating loss of $28.1 million, a GAAP net loss of $52.6 million and a non-GAAP net loss of $16.0 million, with $541.3 million in cash and investments and no debt as of June 30. That balance sheet is what buys the iteration cycles the roadmap requires.
For the broader chips complex, the read-through is that quantum scaling is being converted into a packaging and process-control problem rather than a purely academic one. Fidelity numbers published quarter after quarter — at nine, 36 and 108 qubits — are becoming the sector's equivalent of yield curves: the metric that reveals whether a manufacturing story is actually improving, independent of how many qubits appear in the headline.
